Cocoa — Simpler state machines, inspired by coroutines

1module send (
  input  logic        clk,
  input  logic        rst,
  input  logic        ready,
  input  logic [31:0] payload,
  output logic        valid,
  output logic [31:0] data
8);
  initial forever begin
      // Drive payload onto the bus.
      valid = 1'b1;
      data  = payload;
13 
      // Suspend until the consumer takes the beat.
      @(posedge clk iff ready);
16 
      // Release for one cycle before the next.
      valid = 1'b0;
      @(posedge clk);
  end
21endmodule

1module send (
  input  logic clk,
  input  logic rst,
  input  logic ready,
  input  logic [31:0] payload,
  output logic valid,
  output logic [31:0] data
8);
9 
  typedef enum logic [0:0] { S0, S1 } state_t;
  state_t state, next_state;
12 
  always_comb begin
      unique case (state)
          S0: begin
              // Drive payload onto the bus.
              valid = 1'b1;
              data  = payload;
              if (ready) next_state = S1;
              else      next_state = S0;
          end
          S1: begin
              data  = payload;
              // Release for one cycle before the next.
              valid = 1'b0;
              next_state = S0;
          end
          default: begin
              // Drive payload onto the bus.
              valid = 1'b1;
              data  = payload;
              next_state = S0;
          end
      endcase
  end
36 
  always_ff @(posedge clk) begin
      if (rst) begin
          state <= S0;
      end else begin
          state <= next_state;
      end
  end
44 
45endmodule

1module spi_tx (
  input  logic       clk,
  input  logic       rst,
  input  logic [7:0] tx_byte,
  output logic       cs_n,
  output logic       sclk,
  output logic       mosi,
  output logic       done
9);
  logic [3:0] i;
11 
  initial begin
      // Select the peripheral and clock out eight bits MSB-first.
      cs_n = 1'b0;
      for (i = 0; i < 8; i = i + 1) begin
          mosi = tx_byte[7 - i];
          sclk = 1'b0;
          @(posedge clk);
          sclk = 1'b1;
          @(posedge clk);
      end
22 
      // Release the peripheral and idle forever.
      cs_n = 1'b1;
      done = 1'b1;
      forever @(posedge clk);
  end
28endmodule

1module spi_tx (
  input  logic clk,
  input  logic rst,
  input  logic [7:0] tx_byte,
  output logic cs_n,
  output logic sclk,
  output logic mosi,
  output logic done
9);
10 
  typedef enum logic [1:0] { S0, S1, S2 } state_t;
  state_t state, next_state;
  logic [3:0] i;
14 
  always_comb begin
      unique case (state)
          S0: begin
              done = 1'b0;
              // Select the peripheral and clock out eight bits MSB-first.
              cs_n = 1'b0;
              mosi = tx_byte[7 - i];
              sclk = 1'b0;
              next_state = S1;
          end
          S1: begin
              cs_n = 1'b0;
              mosi = tx_byte[7 - i];
              done = 1'b0;
              sclk = 1'b1;
              if (i < (8) - 1) next_state = S0;
              else next_state = S2;
          end
          S2: begin
              sclk = 1'b1;
              mosi = tx_byte[7 - i];
              // Release the peripheral and idle forever.
              cs_n = 1'b1;
              done = 1'b1;
              next_state = S2;
          end
          default: begin
              done = 1'b0;
              // Select the peripheral and clock out eight bits MSB-first.
              cs_n = 1'b0;
              mosi = tx_byte[7 - i];
              sclk = 1'b0;
              next_state = S0;
          end
      endcase
  end
51 
  always_ff @(posedge clk) begin
      if (rst) begin
          state <= S0;
          i <= 0;
      end else begin
          state <= next_state;
          unique case (state)
              S0: begin end
              S1: begin
                  if (i < (8) - 1) i <= i + 1;
                  else begin
                      i <= 0;
                  end
              end
              S2: begin end
              default: begin end
          endcase
      end
  end
71 
72endmodule

1module mac #(
  parameter int N = 8
3) (
  input  logic               clk,
  input  logic               rst,
  input  logic signed [15:0] a [0:N-1],
  input  logic signed [15:0] b [0:N-1],
  output logic signed [31:0] result,
  output logic               done
10);
  logic [$clog2(N+1)-1:0] i;
12 
  initial begin
      result = '0;
15 
      // One multiply-accumulate per cycle.
      for (i = 0; i < N; i = i + 1) begin
          result = result + a[i] * b[i];
          @(posedge clk);
      end
21 
      // Publish the final value and idle forever.
      done = 1'b1;
      forever @(posedge clk);
  end
26endmodule

1module mac #(
  parameter int N = 8
3) (
  input  logic clk,
  input  logic rst,
  input  logic signed [15:0] a,
  input  logic signed [15:0] b,
  output logic signed [31:0] result,
  output logic done
10);
11 
  typedef enum logic [0:0] { S0, S1 } state_t;
  state_t state, next_state;
  logic [$clog2(N+1)-1:0] i;
15 
  always_comb begin
      unique case (state)
          S0: begin
              done = 1'b0;
              result = '0;
              result = result + a[i] * b[i];
              if (i < (N) - 1) next_state = S0;
              else next_state = S1;
          end
          S1: begin
              result = result + a[i] * b[i];
              // Publish the final value and idle forever.
              done = 1'b1;
              next_state = S1;
          end
          default: begin
              done = 1'b0;
              result = '0;
              result = result + a[i] * b[i];
              next_state = S0;
          end
      endcase
  end
39 
  always_ff @(posedge clk) begin
      if (rst) begin
          state <= S0;
          i <= 0;
      end else begin
          state <= next_state;
          unique case (state)
              S0: begin
                  if (i < (N) - 1) i <= i + 1;
                  else begin
                      i <= 0;
                  end
              end
              S1: begin end
              default: begin end
          endcase
      end
  end
58 
59endmodule

1module debounce #(
  parameter int CLK_PER_MS = 50_000
3) (
  input  logic clk,
  input  logic rst,
  input  logic raw_btn,
  output logic pressed
8);
  initial forever begin
      // Wait for a fresh press.
      pressed = 1'b0;
      @(posedge clk iff raw_btn);
13 
      // Let the line settle for 20 ms.
      repeat (20 * CLK_PER_MS) @(posedge clk);
16 
      // If still held, emit a one-cycle pulse.
      if (raw_btn) begin
          pressed = 1'b1;
      end else begin
          pressed = 1'b0;
      end
      @(posedge clk);
  end
25endmodule

1module debounce #(
  parameter int CLK_PER_MS = 50_000
3) (
  input  logic clk,
  input  logic rst,
  input  logic raw_btn,
  output logic pressed
8);
9 
  typedef enum logic [1:0] { S0, S1, S2 } state_t;
  state_t state, next_state;
  logic [$clog2(20 * CLK_PER_MS)-1:0] cyc0_q;
13 
  always_comb begin
      unique case (state)
          S0: begin
              // Wait for a fresh press.
              pressed = 1'b0;
              if (raw_btn) next_state = S1;
              else      next_state = S0;
          end
          S1: begin
              pressed = 1'b0;
              if (cyc0_q < (20 * CLK_PER_MS) - 1) next_state = S1;
              else next_state = S2;
          end
          S2: begin
              // If still held, emit a one-cycle pulse.
              if (raw_btn) begin
                  pressed = 1'b1;
              end else begin
                  pressed = 1'b0;
              end
              next_state = S0;
          end
          default: begin
              // Wait for a fresh press.
              pressed = 1'b0;
              next_state = S0;
          end
      endcase
  end
43 
  always_ff @(posedge clk) begin
      if (rst) begin
          state <= S0;
          cyc0_q <= '0;
      end else begin
          state <= next_state;
          unique case (state)
              S0: begin end
              S1: begin
                  if (cyc0_q < (20 * CLK_PER_MS) - 1) cyc0_q <= cyc0_q + 1;
                  else begin
                      cyc0_q <= '0;
                  end
              end
              S2: begin end
              default: begin end
          endcase
      end
  end
63 
64endmodule

Simpler state machines, inspired by coroutines.

Examples

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